MAKE uses rules you write along with its default settings to determine how it should compile the files in your project. For example, you can specify when to build your projects with debug information and to compile your .OBJ files only if the date/time stamps of a source file is more recent than the .OBJ itself. If you need to force the compilation of a module, use TOUCH.EXE to modify the time stamp of one of the module’s dependents.  

In an ASCII makefile, you write explicit and implicit rules to tell MAKE how to treat the files in your project; MAKE determines if it should execute a command on a file or set of files using the rules you set up. Although your commands usually tell MAKE to compile or link a set of files, you can specify nearly any operating system command with MAKE.

MAKE [<options>...][<target>[<target>]] 

You must separate the MAKE command and the options and target arguments with spaces.  

When specifying targets, you can use wildcard characters (such as * and ?) to indicate multiple files.  

To display command line help, enter:

make —?

or:

make —h

When you issue a MAKE command, MAKE looks for the file BUILTINS.MAK, a file that you create to contain the default rules for MAKE (use the -r option to ignore the default rules). MAKE looks for this file first in the current directory, then in the directory where MAKE.EXE is stored. After loading BUILTINS.MAK, MAKE looks in the current directory for a file called MAKEFILE or MAKEFILE.MAK (use the -f option to specify a file other than MAKEFILE). If MAKE can’t find the makefile, it generates an error message.  

After loading the makefile, MAKE tries to build only the first explicit target listed in the makefile by checking the time and date of the dependent files of the first target. If the dependent files are more recent than the target file, MAKE executes the commands to update the target.  

If one of the first target’s dependent files is used as a target elsewhere in the makefile, MAKE checks that target’s dependencies and builds it before building the first target. This chain reaction is called a linked dependency.  

If something during the build process fails, MAKE deletes the target file it was building. Use the precious directive if you want MAKE to keep the target when a build fails.  

You can stop MAKE after issuing the MAKE command by pressing Ctrl+Break or Ctrl+C

A makefile is an ASCII file that contains the set of instructions that MAKE uses to build a certain project. Although MAKE assumes your makefile is called MAKEFILE or MAKEFILE.MAK, you can specify a different makefile name with the -f option.  

MAKE either builds the target(s) you specify with the make command or it builds the first target it finds in the makefile. To build more than a single target, use a symbolic target in your makefile.  

Makefiles can contain:

• Comments (precede a comment with a number sign [#])
• Explicit and implicit rules
• Macros
• Directives

A symbolic target forces MAKE to build multiple targets in a makefile. When you specify a symbolic target, the dependency line lists all the targets you want to build (a symbolic target basically uses linked dependencies to build more than one target).  

For example, the following makefile uses the symbolic target AllFiles to build both FILE1.EXE and FILE2.EXE:

AllFiles: file1.exe file2.exe #Note that AllFiles has no commands file1.exe: file1.obj        bcc32 file1.obj file2.exe: file2.obj        bcc32 file2.obj

Rules for symbolic targets

• Do not type a line of commands after the symbolic target line.
• A symbolic target must have a unique name; it cannot be the name of a file in your current directory.
• Symbolic target names must follow the operating system rules for naming files.

You can create the optional file BUILTINS.MAK and store in it the standard rules and macros that you want MAKE to use when it builds the targets in a makefile. To ignore this file when it exists, use the -r MAKE option.  

Here is a sample of a BUILTINS.MAK file:

#
# CodeGear C++ BUILTINS.MAK
#

CC = bcc32
RC = brcc32
AS = tasm32

.asm.obj:
    $(AS) $(AFLAGS) $&.asm

.c.exe:
    $(CC) $(CFLAGS) $&.c

.c.obj:
    $(CC) $(CFLAGS) /c $&.c

.cpp.exe:
    $(CC) $(CFLAGS) $&.cpp

.cpp.obj:
    $(CC) $(CPPFLAGS) /c $&.cpp

.rc.res:
    $(RC) $(RFLAGS) /r $&

.SUFFIXES: .exe .obj .asm .c .res .rc

!if !$d(BCEXAMPLEDIR)
BCEXAMPLEDIR = $(MAKEDIR)\..\EXAMPLES

!endif 

You can use command-line options to control the behavior of MAKE. MAKE options are case-sensitive and must be preceded with either a hyphen (-) or slash (/).  

You must separate the MAKE command and the options and target arguments with spaces. When specifying targets, you can use wildcard characters (such as * and ?) to indicate multiple files. To get command-line help for MAKE, type MAKE -?.  

For example, to use a file called PROJECTA.MAK as the makefile, type:

MAKE -fPROJECTA.MAK

Many of the command-line options have equivalent directives that you can use within the makefile.  

MAKE Macros 

MAKE Directives 

MAKE Rules and Commands